High Performance CMOS Charge Pumps for Phase-locked Loop
نویسندگان
چکیده
منابع مشابه
Design of high-performance CMOS charge pumps in phase-locked loops
Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump by the leakage current, the mismatch, and the delay offset in the P/FD are quantitatively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their performances are compared. The improved design of both the single-en...
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in this paper, a high speed delay-locked loop (dll) architecture ispresented which can be employed in high frequency applications. in order to design the new architecture, a new mixed structure is presented for phase detector (pd) and charge pump (cp) which canbe triggered by double edges of the input signals. in addition, the blind zone is removed due to the elimination of reset signal. theref...
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• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version ...
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ژورنال
عنوان ژورنال: Transactions on Electrical and Electronic Materials
سال: 2015
ISSN: 1229-7607
DOI: 10.4313/teem.2015.16.5.241